Physical Design Engineer- Staff to Sr. Staff
Core
Develop, optimize, and sign off advanced clocking solutions (H-trees, mesh, spine) for next-generation NSP ASIC/SoC designs.
Role type
Staff to Sr. Staff Physical Design Engineer (Clock Architecture)
Builds
High-performance clock distribution structures and methodologies for next-generation NSP chips
Domain
Semiconductor / ASIC Physical Design
Required skills
Clock H-tree design, Clock mesh architecture, Clock spine implementation, SPICE simulation, Transistor-level analysis, Timing closure, Power optimization, Signal integrity analysis, TCL/Python/Perl scripting, Synopsys PrimeTime, Cadence Innovus, Synopsys Fusion Compiler
Preferred skills
None stated
Technologies
Synopsys PrimeTime, Synopsys Fusion Compiler, Cadence Innovus, TCL, Python, Perl, Linux
Responsibilities
Architect and optimize clock distribution structures (H-trees, mesh, spine), Perform SPICE simulation and transistor-level analysis of clock circuits, Drive clock convergence and signoff across multiple modes and corners, Analyze and debug clock skew, jitter, duty-cycle distortion, and signal integrity, Develop and tune clock implementation recipes and automation scripts, Provide technical guidance to block-level physical design engineers, Collaborate with PLL, timing, power, and CAD teams, Support ECO development and tapeout readiness
Seniority
Staff to Sr. Staff, hands-on IC
