CAD Verification Director
Core
Lead verification CAD team to define strategy, architecture, and execution of formal and dynamic verification methodologies ensuring functional integrity of silicon designs.
Role type
Director, Verification CAD Engineer (Senior Leadership)
Builds
Scalable, efficient, and robust CAD solutions for silicon design verification
Domain
Semiconductor / Hardware Engineering / Formal & Dynamic Verification
Required skills
Formal verification (property checking, equivalence checking, model checking), Dynamic simulation (UVM, regression automation), Scripting (Python, Perl, Tcl), SystemVerilog assertions, CI/CD integration, EDA tool integration, Team leadership, Cross-functional collaboration
Preferred skills
AI/ML applications in verification, Constrained-random testing, Functional coverage, Hybrid formal-dynamic flows, Global team management
Technologies
Jasper, VC Formal, UVM, SystemVerilog, Python, Perl, Tcl, Cloud environments
Responsibilities
Define long-term roadmap for CAD verification infrastructure, Lead and grow team of CAD engineers, Architect and deploy formal verification flows, Evaluate and integrate formal tools into production, Optimize simulation performance across compute farms, Develop reusable scripts and frameworks, Collaborate with EDA vendors
Seniority
Director, Strategy & Mentorship
