Mixed-Signal IP Memory & Die-to-Die (D2D) System Engineer - Cork, Ireland
Core
Architect, model, analyze, and validate high-performance memory (LPDDR, DDR, HBM) and Die-to-Die interconnect systems for next-generation SoCs.
Role type
Senior IC system engineer (mixed-signal IP)
Builds
High-speed memory and chip-to-chip communication subsystems for Snapdragon and Dragonfly platforms
Domain
Semiconductor / High-speed interface design
Required skills
System architecture, behavioral/electrical modeling, signal integrity analysis, power integrity analysis, high-speed interface design, simulation environments, silicon validation, trade-off analysis
Preferred skills
SerDes, channel modeling, equalization techniques, timing closure, package/board design, SPICE simulation, UCIe, PCIe, CXL
Technologies
MATLAB, Python, SystemC, Verilog-AMS, SPICE
Responsibilities
Develop and evaluate architectures for next-generation memory and D2D systems; Create simulation environments to evaluate performance, timing, and power; Drive signal integrity and power integrity analysis for high-speed interfaces; Investigate impact of advanced technology nodes and packaging on subsystem performance; Collaborate with analog, digital, package, and validation teams.
Seniority
Mid-to-Senior, hands-on IC
