Senior Lead STA Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products.
Role type
Senior Lead Static Timing Analysis (STA) Engineer
Builds
ASIC blocks and System-on-Chip (SoC) IP
Domain
Semiconductor / ASIC Design / Digital and Analog
Required skills
Static Timing Analysis (STA), Physical Implementation, Timing Constraints, ECO Generation, Perl Scripting, TCL Scripting, Deep Submicron Process Technology, Power Minimization, PPA Optimization
Preferred skills
High Performance and Low Power Implementation Methods, Extreme Critical Path Fixing, Complex Corner Analysis
Technologies
PT, Tempus, GENUS, Innovus, ICC
Responsibilities
Solve extreme critical timing bottleneck paths, prepare complex ECOs for timing convergence across huge sets of corners, minimize power consumption, push PPA to the best possible extent.
Seniority
Senior, hands-on IC
