DFT Staff Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products, with a focus on Design for Test (DFT) concepts and test mode timing constraints.
Role type
Staff IC DFT Engineer (ASIC)
Builds
High performance, low power ASIC blocks and SoCs
Domain
Semiconductor / ASIC Design
Required skills
ASIC design, verification, validation, integration, DFT concepts, scan insertion, ATPG, coverage analysis, transition delay test coverage analysis, test mode timing constraints definition, timing fixes, scripting (Perl, Shell), test vector simulation, equivalence check, DFT DRC rules, RTL linting (Spyglass), ATPG tools (TK, TetraMax), DFT tools (Synopsis TetraMax/DFTMax, Cadence Encounter Test)
Preferred skills
Experience with international teams, adaptability to new tools/methodologies, multi-tasking, problem solving
Technologies
Perl, Shell, Spyglass, TK, TetraMax, Synopsis TetraMax, DFTMax, Cadence Encounter Test
Responsibilities
Define, model, design, optimize, verify, validate, implement, and document IP; perform scan insertion, ATPG, and coverage analysis; define test mode timing constraints and provide timing fixes; simulate test vectors; apply DFT DRC rules and RTL linting
Seniority
Staff, hands-on IC
