Staff SOC Physical Design Engineer
Core
Leads and executes the physical design flow for high-speed DDR, graphics, and micro-architecture SoC products, focusing on power utilization and optimization.
Role type
Staff SOC Physical Design Engineer
Builds
System-on-chip (SoC) products
Domain
Semiconductor / Hardware Design
Required skills
Floor Planning, Clock Tree Synthesis, Place and Route, Power Distribution Network (PDN) design, Timing analysis and closure, Physical verification (LVS, DRC, DFM, DFY), Cross-functional collaboration
Preferred skills
None stated
Technologies
None explicitly listed
Responsibilities
Lead, plan, and synthesize ambiguous or conflicting requirements for the physical design flow; Perform complex responsibilities of the physical design flow including floor planning, clock tree synthesis, place and route, PDN, timing analysis and closure; Perform various physical verification checks (LVS, DRC, design-for-manufacturing & design-for-yield) at chip and block levels; Provide schedules and support cross-functional engineering effort to drive signoff closure for tapeout; Act as a strong contributor at design reviews and project meetings and communicate and implement a development plan.
Seniority
Staff, hands-on IC
