Synthesis Engineer
Core
Physical synthesis and timing closure engineer optimizing digital IC designs for performance and power.
Role type
Senior IC physical synthesis engineer
Builds
High-performance, low-power digital integrated circuits
Domain
Semiconductor hardware design
Required skills
Physical synthesis methodologies, Timing constraints, Static Timing Analysis (STA), Multi-clock domain design, MCMM optimization, Low-power design (UPF), Scripting (Perl/Python/TCL), ECO handling, Formal verification
Preferred skills
None stated
Technologies
Industry standard synthesis tools, UPF, Perl, Python, TCL
Responsibilities
Write timing constraints for synthesis and STA, Perform timing closure and pipelining for performance optimization, Handle ECOs and formal verification, Collaborate with design, DFT, and PD teams for netlist delivery
Seniority
Mid-level, independent contributor with some mentorship
