GPU STA/Timing Engineer (Senior Lead/Staff)
Core
Drive timing signoff and closure for next-generation high-performance GPU designs, collaborating with Architecture, RTL, Physical Design, DFT, and SoC teams.
Role type
Senior Lead/Staff Static Timing Analysis (STA) Engineer
Builds
High-performance GPU silicon products
Domain
Semiconductor hardware engineering (ASIC/SoC)
Required skills
STA, MCMM/MMMC, SDC, timing closure, ECOs, SOCV/AOCV, SI analysis, Synopsys PrimeTime, Tcl/Python scripting, Physical Design flows
Preferred skills
GPU/CPU/AI/ML SoC design experience, advanced technology nodes (5nm and below), Fusion Compiler, ICC2, StarRC, Tempus, Innovus, technical leadership
Responsibilities
Own block-level and full-chip STA signoff, develop and validate timing constraints, perform timing analysis and closure, drive setup/hold/noise/low-power closure, enhance STA methodologies and automation, mentor junior engineers
Seniority
Senior Lead/Staff, hands-on IC with mentorship
