Physical Verification Engineer (Lead/Staff/Sr Staff) - Custom Silicon Group
Core
Lead physical verification sign-off activities for advanced technology nodes to ensure clean sign-off and physical convergence for custom silicon products.
Role type
Senior IC physical verification engineer (custom silicon)
Builds
Custom silicon chips (Digital/Analog/RF/optical systems)
Domain
Semiconductor / Custom Silicon / Hardware Engineering
Required skills
Physical verification sign-off flows, DRC/LVS/Antenna/ERC/PERC/ESD checks, PDK concepts, SVRF rule decks, Calibre, ICV, Innovus, ICC2, Fusion Compiler, advanced technology nodes (2nm/3nm/5nm/7nm/10nm), Tech LEF, Design Rules, Foundry PDKs, debugging in sign-off environments
Preferred skills
Floorplanning, Power Planning, PDN design, automation scripting (TCL/Perl), custom IC design flows, mixed-signal/SOC environments, mentoring
Technologies
Calibre, ICV, Innovus, ICC2, Fusion Compiler, TCL, Perl
Responsibilities
Drive Physical Verification sign-off activities including DRC, LVS, Antenna, ERC, PERC, ESD, and related verification checks for advanced technology nodes; Collaborate closely with Physical Design, Custom Layout, and Foundry teams to ensure clean sign-off and physical convergence; Debug and resolve physical verification violations while driving closure to tape-out; Support methodology development, automation, and flow enhancements for sign-off quality and productivity; Participate in floorplanning, power planning, and PDN reviews to ensure robust physical implementation
Seniority
Staff/Sr Staff, hands-on IC
