SoC Physical Design Engineer (Senior to Principal)
Core
Define, model, design, optimize, verify, validate, and implement IP (block/SoC) development for high performance, high quality, low power products on advanced FinFET nodes.
Role type
Senior to Principal IC Physical Design Engineer
Builds
High performance, low power SoCs and integrated circuits
Domain
Semiconductor / VLSI / ASIC Design
Deliverable
production ML models
Required skills
ASIC physical design, ECO, STA, physical verification, power analysis, floor-planning, place and route, timing/power closure, Python/Tcl scripting, Agentic AI methodologies
Preferred skills
Master's degree in VLSI/Electrical/Computer Engineering, deep expertise in full-chip design flow, power optimization (DVFS, multi-Vt, UPF/CPF), large-scale automation framework architecture
Technologies
FinFET nodes, EDA tools (RTL to GDS Flow), Python, Tcl, Shell
Responsibilities
Define backend design methodology and champion Agentic AI integration into the PD flow, mentor engineers, interface with foundry/EDA vendors/executives, lead design implementation of advanced design rules, conduct complex simulations for PPA optimization, evaluate process flow from synthesis to tape-out, write technical documentation
Seniority
Senior to Principal, hands-on IC with significant decision-making and team guidance
