SoC Physical Design Engineer, Senior Staff
Core
Senior Staff SoC Physical Design Engineer responsible for planning, designing, optimizing, and verifying electronic systems, specifically managing complex subsystems and SoCs to meet Power, Performance, and Area (PPA) requirements.
Role type
Senior Staff IC SoC Physical Design Engineer
Builds
Complex subsystems and System on Chips (SoCs)
Domain
Semiconductor / Hardware Engineering / SoC Physical Design
Required skills
Netlist2GDS flow (Floorplan, PnR, sign-off), Static Timing Analysis (STA), low power design (UPF, power gating), ASIC design flows, automation for PPA optimization, team management
Preferred skills
Experience in lower technology nodes, deep sub-micron technology, multi-voltage domains, IP integration
Technologies
UPF, STA, PnR tools, ASIC flows
Responsibilities
Manage complex subsystems and small teams for project execution and PPA targets; execute complete Netlist2GDS flow including floorplan, place and route, and sign-off convergence; implement low power design strategies; drive automation to improve PPA; integrate IP into SoCs.
Seniority
Senior Staff, hands-on IC with team leadership
