DFT Engineer - Multiple Levels
Core
Design, optimize, verify, and test electronic systems including ASICs, circuits, and packaging to launch cutting-edge products.
Role type
Senior IC DFT Engineer (ASIC)
Builds
ASIC chips and electronic systems
Domain
Semiconductor / Hardware Engineering
Required skills
DFT concepts, scan insertion, ATPG, coverage analysis, transition delay test coverage analysis, test mode timing constraints, scripting (Perl, Shell), test vector simulation, equivalence check, DFT DRC rules
Preferred skills
Genus, Synopsys TetraMax/DFTMax, Cadence Encounter Test
Technologies
Perl, Shell, Spyglass, Tessent, TK, TetraMax, Genus, Synopsys TetraMax/DFTMax, Cadence Encounter Test
Responsibilities
Define test mode timing constraints, provide timing fixes for violations, simulate test vectors, perform RTL linting and ATPG rule checks, collaborate with cross-functional teams on hardware solutions.
Seniority
Senior, hands-on IC
