Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels)
Core
Verification of complex IP blocks for Snapdragon DSP Neural Processing Units (NPU) to accelerate AI machine learning, video, and DSP applications.
Role type
Senior ASIC Design Verification Engineer
Builds
Hardware IP for Qualcomm Snapdragon DSP processors
Domain
Semiconductor / AI & Video Processing
Deliverable
production ML models
Required skills
UVM methodology, SystemVerilog, functional coverage, assertions, constrained-random verification, regression maintenance, testbench architecture, performance testing
Preferred skills
Python, CShell scripting
Technologies
UVM, SystemVerilog, Python, CShell
Responsibilities
Verify complex IP blocks using UVM methodology, resolve architecture/design/verification problems, collaborate with design teams to close coverage, modify testbench components, write tests and assertions, maintain regression suites, contribute to testbench architecture and testplan implementation, support integration and performance testing
Seniority
Senior, hands-on IC
