Physical Design- Sr Staff Engineer
Core
Lead physical design implementation for high-frequency data-path intensive cores, managing floor-planning, place and route, timing closure, and power optimization to deliver PPA-critical solutions.
Role type
Sr Staff IC Physical Design Engineer
Builds
Complex physical design solutions (netlist to final product) for high-frequency data-path intensive cores
Domain
Semiconductor / Hardware Engineering / Physical Design
Required skills
Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, Power optimization, Clocking architecture, Tcl/Perl Scripting, Linux/Unix shell, C
Preferred skills
Advanced STA concepts, Block level PnR convergence, Synopsys ICC2, Cadence Innovus, PTSI/Tempus
Technologies
Synopsys ICC2, Cadence Innovus, PTSI, Tempus
Responsibilities
Perform floor-planning, place and route, CTS, formal verification, and physical verification (DRC/LVS); Optimize timing and power for high-frequency data-path intensive cores; Collaborate with design, DFT, and PNR teams to resolve constraints and verification issues; Manage technical deliverables and project milestones.
Seniority
Sr Staff, hands-on IC
