DFT Engineer, Senior
Core
Define and execute end-to-end DFT strategy (Scan, Boundary Scan/JTAG, Memory/Logic BIST) for semiconductor chips, ensuring high-quality test patterns and yield improvements from pre-silicon verification to silicon bring-up.
Role type
Senior IC DFT Engineer (Semiconductor)
Builds
Testable semiconductor chips and integrated circuits
Domain
Semiconductor hardware design and verification
Required skills
DFT architecture (Scan, JTAG, BIST), RTL insertion & verification, ATPG, MBIST/LBIST design, Python/Tcl/Perl scripting, timing/power aware simulation
Preferred skills
Agentic AI tools for workflow optimization
Technologies
FPGA, DSP, RTL, ATPG tools, Python, Tcl, Perl
Responsibilities
Define DFT strategy including Scan, Boundary Scan/JTAG, and Memory/Logic BIST; Perform RTL insertion and verification; Generate test patterns using ATPG; Design and implement MBIST and LBIST architecture; Collaborate with physical design teams to resolve timing violations; Write automation scripts for DFT flows; Partner with test engineers for silicon bring-up and yield improvement.
Seniority
Senior, hands-on IC
