Physical Design Engineer, Senior Staff - Hod Hasharon
Core
Define and own backend physical design methodology for full-chip and multi-die implementations on advanced TSMC FinFET nodes, integrating Agentic AI into the design flow.
Role type
Senior Staff IC Physical Design Engineer
Builds
High-performance, low-power ASICs and SoCs for next-generation communication and data processing products
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models
Required skills
Full-chip physical design, floorplanning, power delivery network (PDN) design, clock architecture, place-and-route (PnR), static timing analysis (STA), timing closure, signal integrity (SI), power integrity (PI), electromagnetic/IR (EM/IR) analysis, Python scripting, TCL scripting, EDA tool architecture, Agentic AI integration
Preferred skills
Chiplet design, 2.5D/3D IC physical design, advanced packaging technologies, AI/ML-driven EDA tool evaluation
Technologies
TSMC N5/N4P/N3, Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk, Voltus, StarRC, Quantus, Python, TCL
Responsibilities
Architect full-chip physical design strategy including floorplanning, PDN, clock architecture, PnR, and timing closure; Lead critical timing closure efforts (MCMM, OCV, advanced ECO); Oversee signal integrity, power integrity, and reliability analysis; Develop scalable PD flow infrastructure using Python and TCL; Champion Agentic AI adoption for autonomous design exploration and automation; Mentor junior and mid-level engineers; Interface with foundry and EDA vendors.
Seniority
Senior Staff, technical leadership & mentorship
