PMIC Design Verification Sr Engineer
Core
Digital Verification Engineer for Mixed-Signals IPs, ASICs, and Chipsets used in Qualcomm Snapdragon power solutions, focusing on telemetry ADCs, 100W+ charging, 5G power, and high-efficiency power management.
Role type
Senior IC Digital Verification Engineer (Mixed-Signal/Power)
Builds
Digital and mixed-signal IPs, ASICs, and chipsets for Snapdragon power solutions
Domain
Semiconductors / Hardware Engineering / Power Management
Required skills
System Verilog, UVM, constrained-random stimulus, score-boarding, coverage closure, embedded system debugging, RTL design, analog behavioral models
Preferred skills
Python scripting, Perl scripting, analog behavioral model exposure, complex embedded system troubleshooting
Technologies
System Verilog, UVM, Python, Perl, FPGA, DSP, ADC, DC-DC charge pumps, buck converters, linear regulators
Responsibilities
Develop UVM-compliant test-bench architecture; create constrained-random stimulus; perform score-boarding and coverage closure; debug complex embedded systems including SOCs and firmware; plan verification tasks and mitigate project risks; partner with international teams from system definition to high-volume OEM launches.
