Physical Design Engineer, Staff
Core
Drive the backend physical design process for high-performance, low-power ASIC/SoC development, including floorplanning, place & route, timing closure, and signoff.
Role type
Staff Physical Design Engineer (ASIC/SoC)
Builds
Digital and/or analog IP blocks and System-on-Chip (SoC) products
Domain
Semiconductor / ASIC Design
Required skills
Physical Design, Floorplanning, Place & Route, Clock Tree Synthesis, Static Timing Verification, DRC/LVS/ERC Verification, Power Integrity Analysis, Scripting
Preferred skills
Low-Power Design, SoC Design, Advanced Technology Node
Technologies
EDA tools, LLM
Responsibilities
Drive the backend process through the entire implementation flow, Perform floor-planning, block partitioning, and power planning, Support front-end team in PPA optimization trials, Place & Route with focus on power and area optimization, Perform Clock Tree Synthesis/Inspection/Optimization, Perform static timing verification and timing closure, Perform physical verification and fixing (DRC, ANT, DFM, LVS, ERC), Perform EM/IR signoff and address power integrity issues.
