DFT Engineer, Principal
Core
Architecting and developing DFT methodologies, flows, and verification solutions for complex SoC, ASIC, and IP designs to ensure testability and quality.
Role type
Principal DFT Engineer (SoC/ASIC)
Builds
Integrated RTL-centric DFT environments, automated verification test benches, scan insertion flows, and ATPG retargeting procedures for world-class chips.
Domain
Semiconductor hardware engineering (SoC, ASIC, IP)
Required skills
DFT methodology design, RTL design (Verilog/VHDL/SystemVerilog), ATPG, scan insertion, BIST techniques, static timing analysis, EDA tool scripting (Perl/TCL/Python), SoC design experience
Preferred skills
CoWoS design integration, zero delay/SDF annotated test sequence simulation, CAD automation
Technologies
Siemens, Synopsys, Cadence EDA tools, JTAG, iJTAG, SystemVerilog, Perl, TCL, Python
Responsibilities
Develop and maintain DFT flows across business units, architect shift-left DFT environments, write automated RTL for advanced DFT features, create verification test benches, build scan insertion flows, write static timing constraints and waivers.
Seniority
Principal, hands-on IC
