NPU/AI Processor Synthesis (Design implementation) - Staff Engineer
Core
Drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators (NPUs) used in next-generation SoCs.
Role type
Staff IC ASIC synthesis engineer
Builds
NPU IPs and subsystems for next-generation SoCs
Domain
Semiconductor hardware design (ASIC)
Deliverable
production ML models
Required skills
RTL synthesis, timing closure, Synopsys Design Compiler/Fusion Compiler, Cadence Genus, PrimeTime, UPF/low-power flows, TCL/Python/Perl scripting, clocking architecture, SDC constraints
Preferred skills
AI/ML accelerator experience, advanced technology nodes (5nm/4nm/3nm), physical-aware synthesis, hierarchical design, tapeout history
Responsibilities
Own RTL-to-gate synthesis and timing closure; Develop and maintain synthesis flows, constraints, and automation; Drive pre-layout and post-layout timing closure; Optimize designs for PPA targets; Create and validate timing constraints (SDC); Collaborate with RTL, DFT, STA, and Physical Design teams; Perform quality checks (LEC, CDC, lint, low-power verification); Analyze and improve synthesis QoR via scripting; Support tapeout activities
Seniority
Staff, hands-on IC
