SoC HW Architecture
Core
Define hardware architecture for next-generation SoC infrastructure IPs (Interconnect, System Cache, Memory controllers, System MMU) with ARM Architecture enabled.
Role type
Senior SoC HW Architecture Engineer
Builds
Infrastructure IP components for Qualcomm SoCs
Domain
Semiconductor / SoC Design
Required skills
Multi-die/chiplet architectures, Interconnect protocols (NOC), SOC infrastructure IP (NOC, SMMU, Caches), Quality of Service/Clocks/Power/Security architectures, HW-SW interfaces, RTL design, Performance modeling
Preferred skills
Platform System Architecture (ARM/X86/RISC-V), Industry standards (PCIe, CXL, USB, UFS, MIPI, UCIe), ARM Advanced Technology (Security, RAS, MPAM, Memory Tagging), Data Science/ML, Functional Safety
Technologies
ARM, PCIe, CXL, USB, UFS, MIPI, UCIe, RTL
Responsibilities
Define HW architectures based on Product Requirements and HW-SW interfaces, Drive innovative technology definitions, Collaborate on HW-SW feature trade-offs, Understand complete silicon HW end-2-end design flow
Seniority
Senior, hands-on IC
