SoC DFT Lead, Director
Core
Lead DFT strategy and implementation for complex SoCs, driving architecture and methodology for scan, BIST, and boundary scan to ensure robust test coverage and high-quality silicon.
Role type
Director, SoC DFT Lead
Builds
SoC test infrastructure and methodologies for Qualcomm hardware products
Domain
Semiconductor / Hardware Engineering / SoC Design
Required skills
DFT strategy, Scan insertion, ATPG, MBIST, LBIST, JTAG, Test Coverage Analysis, Verilog/System Verilog, Scripting (TCL, Perl, Python), Cross-functional collaboration, Technical leadership
Preferred skills
Operating budget management, Project financials, Technical leadership with direct reports
Technologies
Synopsys, Mentor Tessent, Cadence Modus
Responsibilities
Lead DFT strategy and implementation for complex SoCs, Drive architecture and methodology for scan, BIST, and boundary scan, Collaborate with design, verification, and physical implementation teams, Mentor and guide engineers, Perform Test Coverage Analysis and optimization
Seniority
Director, strategic leadership with supervision of supervisors
