NPU Design implementation (Synthesis) Principal/Manager
Core
Lead RTL-to-gate-level synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs, optimizing for Performance, Power, and Area (PPA).
Role type
Principal/Manager NPU Synthesis Lead
Builds
High-quality netlists for advanced technology nodes for SoCs
Domain
Semiconductor / ASIC Design / AI Hardware
Deliverable
production ML models
Required skills
RTL-to-gate synthesis, Timing closure, PPA optimization, UPF/CPF low-power flows, Tcl/Perl/Python scripting, SDC constraint management, LEC/CLP verification
Preferred skills
Advanced nodes (5nm/3nm), hierarchical synthesis, physical-aware flows, tape-out experience for NPU/DSP
Technologies
Synopsys Design Compiler, Cadence Genus, PrimeTime, Spyglass, UPF, CPF
Responsibilities
Lead synthesis flows for NPU IP, drive timing closure across process corners, apply physical-aware synthesis for PPA targets, validate SDC constraints, mentor junior engineers, collaborate with RTL/Physical design teams
Seniority
Principal/Manager, hands-on IC with team leadership
