Senior Manager/ Manager - Memory Circuit Design
Core
Lead verification efforts and guide teams in verifying complex full-chip gate-level custom memory designs (DDR4/5, LPDDR4/5) operating at high speeds.
Role type
Senior Manager, Memory Circuit Design Verification
Builds
Advanced DRAM and emerging memory products
Domain
Semiconductor / Memory / Verification
Required skills
Team leadership, CMOS analysis, Gate-level circuit analysis, SPICE simulation, Verilog simulation
Preferred skills
SystemVerilog, PLI coding, UVM Test Bench, DRAM/SRAM verification, AMS verification, Co-simulation
Technologies
DDR4, LPDDR4, DDR5, LPDDR5, SPICE, Verilog, SystemVerilog, UVM
Responsibilities
Guide verification direction for projects, Lead cross-site methodology development, Advise senior management on technical issues, Establish best-known methods, Provide pre-silicon simulation/debugging support, Develop test cases and vectors for coverage analysis
Seniority
Senior Manager, hands-on IC leadership
