Staff Engineer, ASIC IP STA
Core
Staff Engineer responsible for post-layout Static Timing Analysis (STA) signoff and timing closure of high-speed interface IPs (DDR PHY, ONFI PHY, IO Expander) for SoC integration.
Role type
Staff IC ASIC Physical Design Engineer (STA)
Builds
High-performance memory and storage interface IPs (DDR, NAND, NOR) for data centers, AI, 5G, and mobile applications.
Domain
Semiconductor / VLSI / Memory & Storage
Required skills
Static Timing Analysis (STA), Cadence Tempus, MMMC timing analysis, Liberty (.lib) and ETM model generation, SDF generation, Gate-Level Simulation (GLS), TCL/Python scripting, OCV/AOCV/POCV methodologies, timing constraint development and validation
Preferred skills
Advanced-node high-frequency design (LPDDR/DDR), AMS/Digital-on-Top IP flows, AI/ML-enabled EDA methodologies, Agentic AI workflows
Technologies
Cadence Tempus, Genus, Innovus, TCL, Python, SDF, .lib, ETM
Responsibilities
Perform post-layout STA signoff and timing closure for high-speed interface IPs; develop and validate timing constraints including clocks, generated clocks, and exceptions; generate and correlate Liberty/ETM timing models; support verification teams with SDF and GLS; debug timing violations across functional, scan, and DFT modes; automate timing flows using TCL/Python; collaborate with IP Design, Synthesis, and Physical Design teams
Seniority
Staff, hands-on IC with mentorship
