DFT Engineer (Senior to Staff level)
Core
Design, optimize, verify, and test electronic systems including Digital/Analog/RF/optical systems, circuits, and packaging to launch cutting-edge products.
Role type
Senior to Staff DFT Engineer (Hardware/SoC)
Builds
Integrated RTL-centric DFT environments, ASICs, SoC designs, and test systems for Qualcomm business units.
Domain
Semiconductor hardware engineering, SoC design, DFT methodologies
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT EDA tools (Siemens, SNPS, Cadence), Verilog/VHDL/SystemVerilog, JTAG standards (1149.1/1149.6/1500), iJTAG, BIST techniques, RTL design, scan insertion, ATPG, static timing constraints, TCL/Python scripting
Preferred skills
Custom DFT logic integration for CoWoS designs, CAD automation, de-Perl techniques
Technologies
Siemens, SNPS, Cadence, RTL, JTAG, iJTAG, BIST, ATPG, TCL, Python, Perl
Responsibilities
Architect integrated RTL-centric DFT environments; write and automate RTL for advanced DFT features; develop automated verification test benches; build IP/block and SoC level scan insertion flows; write static timing constraints and devise timing check flows
Seniority
Senior to Staff, hands-on IC
