Design For Test Engineer (DFT) - Cork, Ireland
Core
Design and implement Design for Test (DFT) and Design for Debug (DFD) techniques for low power, high performance System on Chips (SoCs) to reduce test costs and enhance yield.
Role type
ASIC DFT Engineer
Builds
High performance, low power SoCs for Qualcomm products
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT/DFD techniques, Core-based test methodology, Scan isolation, Fault modelling (Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ), JTAG, MBIST, Scan Compression, ATPG, Fault Simulation, at-speed testing, Silicon bring-up and debug, Formal verification, Low power design (UPF), Logic Design, RTL (VHDL/Verilog), Static timing analysis, Simulation tools, Scripting (TCL/Python/Perl)
Preferred skills
Experience with Synopsys Tetramax, Cadence Encounter Test, Siemens Tessent, Synopsys DFTCompiler/Fusion Compiler, VCS, ModelSim, Conformal Low Power
Technologies
Synopsys Tetramax, Cadence Encounter Test, Siemens Tessent, Synopsys DFTCompiler, Fusion Compiler, VCS, ModelSim, Conformal Low Power, LEC, Formality
Responsibilities
Implement advanced DFT/DFD techniques for SoCs, Deploy DFT methodologies to reduce test cost and increase production quality, Validate DFT features on ATE during silicon bring-up, Utilize formal verification tools for design validation
Seniority
Mid-Senior IC Engineer
