Senior Engineer ,DPG LPDDR Verification
Core
Lead verification and end-to-end analysis of sophisticated full-chip gate-level custom designs for advanced low-power memory technologies (DDR5, LPDDR5, DDR6, LPDDR6) operating at high speeds up to 9600MT/s.
Role type
Senior IC verification engineer (memory/DRAM)
Builds
Pre-silicon full chip designs for DRAM and emerging memory architectures
Domain
Semiconductor / Memory / Hardware Verification
Required skills
Gate-level simulation (with delays), Logic schematic analysis, CMOS circuit design analysis, Verilog simulation, Spice simulation, Python scripting, Timing analysis (Setup/Hold, critical data path), Test bench development, Regression analysis, AI-based automation for verification
Preferred skills
Experience with AI-assisted tools for verification productivity, Experience with DRAM/SRAM architectures
Technologies
Verilog, Spice, Python, Gate-level simulators
Responsibilities
Guide and set direction for verification efforts, Simulate and debug pre-silicon full chip designs, Develop test cases and stimulus to increase functional coverage, Participate in developing verification methodology and environments, Collaborate on developing new verification flows, Maintain test benches and run regressions for coverage analysis, Identify verification pain points suitable for AI-based automation
Seniority
Senior, hands-on IC
