STAFF ENGINEER, DDEG Design Methodology
Core
Lead verification and end-to-end analysis for sophisticated full-chip gate-level custom designs in DDR4, LPDDR4, DDR5, and LPDDR5 technologies, leveraging AI-based tools and automation frameworks.
Role type
Staff Engineer, Digital/Mixed-Signal Verification (Memory)
Builds
High-speed DRAM and emerging memory architectures (up to 6400MT/s)
Domain
Semiconductor / Memory Storage / Digital Design
Deliverable
production ML models
Required skills
SystemVerilog, UVM, SPICE, gate-level circuit analysis, AI tool validation, test bench development, mixed-signal verification
Preferred skills
Perl/Python scripting, Real Number Models, prior DRAM experience
Technologies
Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Accelerate verification cycle time using AI/automation; Develop and maintain test benches and vectors for coverage analysis; Simulate, analyze, and debug pre-silicon block/full-chip designs; Guide new team members; Validate AI outputs against specs and simulations.
Seniority
Staff, hands-on IC with mentorship
