SR ENGINEER, DDEG Design Methodology
Core
Senior verification engineer responsible for end-to-end analysis, simulation, and debugging of full-chip gate-level custom DRAM designs using AI-based tools and automation.
Role type
Senior IC verification engineer (DRAM memory)
Builds
High-speed DDR4/LPDDR4/DDR5/LPDDR5 memory chips operating up to 6400MT/s
Domain
Semiconductor / Memory / Digital & Mixed-Signal Verification
Required skills
SystemVerilog, UVM, SPICE, gate-level circuit analysis, AI tool validation, test-bench development, regression analysis, mixed-signal verification
Preferred skills
Real Number Models, Perl/Python scripting, DRAM/SRAM domain knowledge, AMS verification, co-simulation
Technologies
Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Accelerate verification cycles using AI/automation; develop and maintain SV/UVM testbenches; debug pre-silicon block/full-chip designs; validate AI outputs against specs and simulations; collaborate globally on verification methodology.
Seniority
Senior, hands-on IC
