Engineer, DDEG Design Methodology
Core
Develop verification methodologies, test benches, and test vectors for DRAM and emerging memory architectures using simulation tools and AI-based automation to accelerate verification cycles and improve debug efficiency.
Role type
IC verification engineer (DRAM design)
Builds
Pre-silicon block level and full chip designs for DRAM and emerging memory products
Domain
Semiconductor / Memory / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRAM design verification, test bench development, test vector creation, simulation analysis, debugging pre-silicon designs, functional coverage analysis, SPICE simulation, Verilog simulation, gate level circuit analysis, CMOS circuit understanding, AI-based tool usage, automation frameworks
Preferred skills
Agentic AI workflows, advanced verification techniques, international collaboration
Technologies
SPICE, Verilog, simulation tools, AI-based verification tools
Responsibilities
Develop and maintain test benches and test vectors using simulation tools; run regressions for coverage analysis and improvements; simulate, analyze, and debug pre-silicon full chip designs; contribute to developing verification methodology and environments; leverage AI-based tools and automation to accelerate verification cycles; increase functional coverage for DRAM and emerging memory architectures.
Seniority
Individual Contributor
