Engineer, DDEG Design Methodology
Core
Develop verification methodologies, test benches, and test vectors for DRAM and emerging memory architectures using simulation tools and AI-based automation to accelerate verification cycles and improve debug efficiency.
Role type
Senior IC verification engineer (DRAM design)
Builds
Pre-silicon block level and full chip designs for DRAM and emerging memory products
Domain
Semiconductor / Memory / Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRAM design verification, Test-Case/Test-Bench development, Simulation and debugging, Agentic AI workflows, Functional coverage analysis, SPICE simulation, Verilog simulation, Gate level circuit analysis, CMOS circuit understanding
Preferred skills
Advanced verification techniques, International collaboration, Automation framework development
Technologies
SPICE, Verilog, Agentic AI Flow, Simulation tools
Responsibilities
Develop and maintain test benches and test vectors using simulation tools; Run regressions for coverage analysis and improvements; Simulate, analyze, and debug pre-silicon full chip designs; Participate in developing verification methodology and environments for advanced DRAM products; Leverage AI-based tools to accelerate verification cycle time and improve debug efficiency.
Seniority
Senior, hands-on IC
