Engineer - IP Verification
Core
Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon IP designs for DRAM and emerging memory architectures.
Role type
Senior IC analog/mixed-signal verification engineer
Builds
Pre-silicon IP designs for DRAM and emerging memory products
Domain
Semiconductor memory (DRAM) and mixed-signal circuit design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal circuit understanding, SPICE testbench creation, SystemVerilog/UVM verification, PSL assertions, Perl/Python scripting, Virtuoso, Hspice, Xcellium, Simvision, Waveview
Preferred skills
Verilog A/MS/RVM model writing, COSIM/mixed-signal verification environment setup, AI tools and workflows, DRAM memory domain experience
Technologies
Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview, SystemVerilog, UVM, PSL, Perl, Python
Responsibilities
Develop test cases and stimulus to increase functional coverage for DRAM and emerging memory architectures; Develop and maintain test benches and test vectors using simulation tools; Run regressions for coverage analysis and improvements; Co-work with international colleagues on developing new verification flows; Participate in developing verification methodology and verification environments
Seniority
Mid-level, hands-on IC
