Staff Engineer - Design Verification
Core
Lead design verification activities for DRAM products, leveraging AI-based tools and automation to accelerate verification cycles and improve debug efficiency.
Role type
Staff Engineer, Design Verification (DRAM)
Builds
Pre-silicon block level and full chip designs for DRAM and emerging memory architectures
Domain
Semiconductor / Memory Storage / Digital & Mixed Signal Verification
Deliverable
production ML models | product features
Required skills
UVM, SystemVerilog (SV), Digital/Mixed Signal Verification, Test Bench Development, Regression Analysis, Perl scripting, Python scripting
Preferred skills
Experience with Agentic AI workflows, AI-based verification tools, Industry standard simulators (Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice)
Technologies
UVM, SystemVerilog, Perl, Python, Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Develop and maintain test benches/test vectors using simulation tools; Run regressions for coverage analysis; Collaborate with CAD, EDA, and software teams to integrate AI-driven flows into verification environments; Assist in developing new product opportunities by supporting overall verification activities.
Seniority
Staff, hands-on IC with strategic collaboration
