Staff Physical Design Engineer, HBM
Core
Drive backend implementation of high-performance, low-power digital logic for advanced memory products (HBM) from netlist to GDSII, focusing on timing closure, power integrity, and manufacturability.
Role type
Staff Physical Design Engineer (Digital)
Builds
High-performance, low-power digital logic for HBM and advanced memory products
Domain
Semiconductor / Memory / Digital Physical Design
Required skills
RTL-to-GDSII physical design flow, floorplanning, place & route, clock tree synthesis, timing analysis and closure, power integrity analysis, scripting (TCL, Python, Perl, Shell), cross-functional collaboration
Preferred skills
Advanced technology nodes, high-frequency/high-density designs, memory/HBM/datapath-intensive designs, 3D-IC technology and packaging, device physics
Technologies
EDA tools, STA tools, UPF/CPF, DRC/LVS/ANT/DFM, TCL, Python, Perl, Shell
Responsibilities
Execute physical design implementation from synthesized netlist through GDSII including floorplanning, placement, clock tree synthesis, routing, and physical signoff; Perform and drive timing closure across multiple modes, corners, and scenarios; Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues; Develop and refine floorplans, power grids, and clocking strategies; Collaborate with RTL designers to influence partitioning, constraints, and micro-architecture decisions; Implement and validate low-power design techniques including power gating and UPF/CPF-based power intent; Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows; Drive functional and timing ECOs to meet design targets; Use scripting and automation to improve productivity and flow robustness; Interface with EDA vendors and internal CAD teams to debug tool issues and improve methodologies.
Seniority
Staff, hands-on IC with mentorship
