Principal Design Verification Engineer, HBM
Core
Verify IP, subsystem, full-chip, and system-level HBM and DRAM designs to ensure functional correctness, performance, power efficiency, and product quality.
Role type
Principal Design Verification Engineer (HBM/DRAM)
Builds
HBM and DRAM memory products for high-performance computing applications
Domain
Semiconductor / Memory / High-Performance Computing
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, assertion-based verification (SVA), coverage-driven verification, AI-assisted verification workflows, complex design debugging, mixed-signal verification methodologies
Preferred skills
HBM/DRAM architecture and protocol operation, analog and digital simulation (HSPICE, FineSim), Python/Perl scripting for automation, scalable verification infrastructure development
Technologies
UVM, SystemVerilog, HSPICE, FineSim, Verilog, Python, Perl
Responsibilities
Develop comprehensive verification plans from architecture and functional specifications; Create, enhance, and maintain verification environments, UVM testbenches, test suites, and automated regression infrastructures; Define and execute coverage-driven verification strategies; Lead debug and root-cause analysis of complex design issues; Drive continuous improvements in verification methodologies, automation, regression efficiency, and AI-assisted verification workflows; Lead verification efforts for major HBM development programs and mentor engineers
Seniority
Principal, technical leadership & mentorship
