Staff DFT Engineer
Core
Architect, implement, and validate innovative Design for Test (DFT) techniques on System-on-Chips (SoCs) and sub-systems for client, datacenter, automotive, and IoT lines of business.
Role type
Staff DFT Engineer
Builds
SoCs and sub-systems with integrated DFT logic, scan insertion, and test patterns for silicon characterization.
Domain
Semiconductor / SoC Design / Test Engineering
Required skills
Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, Verilog RTL, TCL, Perl, Cadence, Synopsys DFT tools
Preferred skills
SoC multi-clock domain architectures, low power build practices, Arm IP (Cortex CPUs, Mali GPUs, AMBA, CoreLink, CoreSight), high performance build timing constraints, 2.5D and 3D test (via careerplan.io/jobs/99691516816-staff-dft-engineer-at-arm)
Technologies
Siemens, Cadence, Synopsys, Verilog, TCL, Perl, JTAG, ATPG, ATE
Responsibilities
Insert DFT logic into SoCs and validate features using simulation tools; Run RTL and gate-level simulations; Generate ATPG patterns and debug coverage; Develop and validate DFT timing requirements; Collaborate on RTL insertion, synthesis, scan insertion, place-and-route, and timing closure; Participate in ATE test pattern validation and silicon debug; Collaborate on silicon characterization and validation.
Seniority
Staff, hands-on IC with 10+ years experience
