Semiconductor Principal Design Engineer
Core
Lead the design, layout, and optimization of datapath circuits and TSV interfaces for NAND flash memory products, driving architectural decisions for high-speed, low-power memory solutions.
Role type
Principal IC Design Engineer (Memory/TSV)
Builds
High-performance NAND flash memory chips with advanced 3D-stacked architectures
Domain
Semiconductor / Memory / 3D-Stacked Technology
Required skills
TSV interface circuit design, high-speed memory interface design (DDR/HBM), timing analysis, signal integrity analysis, power integrity analysis, DFT circuit design, parallel bus architecture, clock distribution, CMOS device modeling, AI tool application for design workflow
Preferred skills
Chip-level PDN optimization, CMOS device reliability, CMOS BSIM modeling, physical design, signal/power integrity, power delivery network design
Technologies
Verilog, TSV, NAND, DRAM, HBM, DDR, LPDDR, CMOS, BSIM, PDN, DFT
Responsibilities
Design and optimize TSV interface circuits including Rx/Tx, impedance matching, and timing margin analysis; Develop and characterize TSV electrical models and define circuit design constraints; Define and implement signal and power integrity requirements for TSV channels; Design and verify TSV-specific DFT circuits including loopback and redundancy logic; Interface with process technology and DTCO teams to optimize design rules and layout strategies; Develop and execute functional verification plans including full chip simulation and Verilog regression; Architect the data path from page buffer to TSV output interface managing parallelism; Develop clocking and synchronization strategies for highly parallel internal buses; Implement column redundancy and lane repair schemes; Define timing budgets and perform timing analysis under PVT variations; Support post-silicon validation, debug, and tape-out revisions; Collaborate with packaging and assembly teams on TSV reliability constraints.
Seniority
Principal, hands-on IC design leader
