SENIOR ENG-HIG-HBM-LAYOUT
Core
Build and develop critical analog, mixed-signal, and custom digital blocks for High Bandwidth Memory (HBM) chips, providing full chip-level integration support and tapeout of PWF Reticles.
Role type
Senior IC Layout Engineer (Analog/Mixed-Signal)
Builds
Advanced memory and semiconductor technologies for AI and high-performance computing solutions
Domain
Semiconductor / Memory / VLSI
Required skills
Analog/custom layout development, Cadence VLE/VXL, Mentor Calibre DRC/LVS, TSV build, memory build architectures, physical verification, project management, team leadership
Preferred skills
Multiple tape-out support experience, managing multiple layout projects
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Build and develop critical analog, mixed-signal, custom digital blocks; Build and tapeout PWF Reticles; Collaborate with Scribe Build team on Advanced Packaging; Engage in TSV build with HIG-HBM DTPCO teams; Perform layout verification (LVS/DRC/Antenna checks); Guide less experienced team members in sub-block-level layouts
Seniority
Senior, hands-on IC with leadership responsibilities
