HBM 3D Power Delivery Network (PDN) Engineer
Core
Design, analyze, and optimize power delivery networks (PDN) for next-generation HBM products, ensuring robust power integrity and reliability across die-package-system interactions.
Role type
Senior IC HBM Power Delivery Network (PDN) Engineer
Builds
HBM memory stacks and high-performance ASICs
Domain
Semiconductor / Memory / 3D Heterogeneous Integration
Deliverable
production ML models | product features
Required skills
PDN design and analysis, EM/IR analysis, Spice-based simulation, 3D PDN modeling, physical design flow knowledge, RTL-to-GDSII signoff, debugging complex power issues
Preferred skills
HBM/DRAM memory-centric SoC design, 3DIC power delivery challenges, die-package-system co-design, advanced packaging (2.5D/3D), transient/vector-based power analysis, JEDEC standards
Technologies
Cadence RedHawk, Ansys Totem
Responsibilities
Design SoC-level and HBM-cube-level power grids and routing; Perform EM/IR analysis and optimization; Collaborate on floorplanning and placement for efficient PDN; Drive power integrity closure across multi-mode scenarios; Co-optimize die-package-system interactions; Develop and validate power models; Influence power-aware design decisions; Support signoff and reliability verification; Debug PDN issues pre- and post-silicon; Improve PDN methodologies via automation
Seniority
Senior, hands-on IC
