MTS HIG-HBM-LAYOUT
Core
Lead end-to-end layout execution and full-chip technical decisions for analog, mixed-signal, and custom digital blocks in HBM products.
Role type
Senior IC physical design engineer (HBM layout)
Builds
High-bandwidth memory (HBM) chips
Domain
Semiconductor / Memory / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal layout, full-chip integration, floor planning, manual routing, LVS, DRC, Antenna checks, team leadership, project planning, AI/automation adoption
Preferred skills
Experience with Cadence VLE/VXL, Calibre DRC/LVS, Tape-out leadership
Technologies
Cadence VLE/VXL, Calibre
Responsibilities
Lead end-to-end layout execution of analog, mixed-signal, and custom digital blocks; Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR; Perform and oversee layout verification activities including LVS, DRC, and Antenna checks; Lead and mentor the layout team; Drive innovation and productivity improvements using AI/automation; Collaborate with global cross-functional teams; Support customer and product integration needs
Seniority
Senior, hands-on IC with team leadership
