Senior Package Design Engineer
Core
Lead co-design from silicon to system for advanced semiconductor packages, optimizing die floorplans, interconnection schemes, and package architectures for AI, data center, mobile, and automotive applications.
Role type
Senior IC package design engineer (semiconductor)
Builds
Advanced memory packages (DRAM) for AI, data centers, mobile, and edge devices
Domain
Semiconductor industry, advanced packaging
Required skills
Advanced package EDA tools (Cadence Allegro, Xpedition), flip chip/wire bond interconnects, substrate stack-ups, high-density routing, SI/PI simulation integration, OSAT collaboration, DFM/DFMEA
Preferred skills
Advanced DRAM technologies (LPDDR, HBM, GDDR), TSV stacking, micro-bump layout, Chip-Package Interaction (CPI) analysis, 2.5D/3D-IC, FOWLP, SiP, AutoCAD/Autodesk Mechanical, co-design leadership
Technologies
Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, Siemens/Mentor Xpedition, AutoCAD, Autodesk Mechanical
Responsibilities
Partner with silicon design and customers to define new product concepts; optimize die floorplans and package architectures; lead floorplanning, routing, and layout; conduct DFM reviews and feasibility studies; partner with SI/PI teams for simulation integration; collaborate with OSAT partners to define design rules and advance routing methodologies.
Seniority
Senior, hands-on IC
