Senior Engineer - HBM Design for Test (DFT)
Core
Definition, implementation, integration, and support of Design for Test (DFT) solutions for HBM core and base dies.
Role type
Senior IC DFT Engineer (HBM)
Builds
HBM memory products (core and base die)
Domain
Semiconductor / Memory / HBM
Required skills
DFT architecture, DFT implementation, DFT verification, silicon bring-up, tape-out support, debug, HBM/DRAM memory architecture, design specifications, reuse/standardization of DFT logic
Preferred skills
DFT verification coverage methodologies, manufacturing test flows, Analog/Digital design and verification in Cadence environments
Technologies
Cadence
Responsibilities
Implement and integrate DFT features for assigned HBM core and base die designs; Contribute to development and maintenance of DFT specifications and guidelines; Collaborate with Design, Product, Test, and Verification teams to translate requirements into DFT implementations; Identify, debug, and resolve DFT-related issues during build execution and silicon bring-up; Document DFT implementations and procedures.
Seniority
Senior, hands-on IC
