MTS DRAM ASIC Architect
Core
Define next-generation DRAM architectures incorporating advanced CMOS-based logic die technologies to enable higher integration, observability, reliability, power efficiency, and security.
Role type
Senior IC DRAM ASIC Architect
Builds
Next-generation DRAM products (LPDDR, DDR, HBM) with integrated logic die capabilities
Domain
Semiconductor / Memory / ASIC Design
Deliverable
production ML models | product features
Required skills
DRAM architecture, ASIC/SoC architecture, functional partitioning, architectural tradeoff analysis, high-speed I/O, PHY architectures, clocking systems, die-to-die interfaces
Preferred skills
DDR5/DDR6, LPDDR5/LPDDR6, HBM, GDDR, TSV-based architectures, hybrid bonding, 2.5D/3D packaging, CMOS technologies, analog/mixed-signal circuit concepts, heterogeneous integration, AI-assisted coding techniques
Technologies
LPDDR, DDR, HBM, GDDR, TSV, hybrid bonding, 2.5D/3D packaging
Responsibilities
Define functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms; Architect high-performance interfaces between DRAM die and logic die; Identify and evaluate system, interface, reliability, test, management, and control functions for logic-die implementations; Define scalable CMOS logic-die architectures and subsystem solutions using custom, semi-custom, and standard IP solutions; Perform architectural tradeoff analysis covering area, power, latency, yield, testability, reliability, and product scalability; Influence roadmaps for advanced memory system capabilities
Seniority
Senior, hands-on IC