DRAM Architect – Principal Engineer | MTS - TPG
Core
Develop system-level solutions, tools, and methodologies to optimize DRAM performance, power efficiency, and cost while pioneering new memory features.
Role type
Principal DRAM Architect (MTS level)
Builds
High-quality, reliable, and power-efficient DRAM solutions for global markets
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models | product features
Required skills
DRAM architecture design, system-level optimization, power/performance/cost trade-off analysis, cross-functional collaboration, technical mentorship
Preferred skills
Advanced memory technology expertise (LPDDR5/6, DDR5/6, GDDR6/7, HBM3E/4), industry trend analysis, creative problem-solving
Technologies
LPDDR5/6, DDR5/6, GDDR6/7, HBM3E/4
Responsibilities
Develop system-level solutions and tools for DRAM optimization; Collaborate with multi-functional teams to implement innovative memory solutions; Analyze system behavior to drive data-driven optimizations; Drive architectural innovation for current and future DRAM generations; Mentor team members through training and technical guidance
Seniority
Principal, hands-on IC with strategy & mentorship