Staff Engineer, HIG HBM Layout
Core
Design and development of critical analog, mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Staff IC Layout Design Engineer
Builds
Custom analog/mixed-signal blocks (PLL, ADC, DAC, LDO, etc.) and full chip layouts for HBM
Domain
Semiconductor / VLSI / Memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, Mixed-signal layout design, Custom digital block layout, LVS/DRC/Antenna verification, Layout hierarchy management, Tape-out support, Project scheduling, Team leadership
Preferred skills
Experience with Temperature sensor, Charge Pump, Current Mirrors, Comparator, Differential Amplifier
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Design and develop critical analog, mixed-signal, custom digital block and full chip level integration; Perform layout verification like LVS/DRC/Antenna, quality check and documentation; Guide junior team-members in their execution of Sub block-level layouts & review their work; Manage multiple layout projects ensuring quality checks at all stages
Seniority
Senior, hands-on IC with team leadership