Engineer, HIG HBM Layout
Core
Design and development of critical analog, mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Senior IC Layout Design Engineer (Analog/Mixed-Signal)
Builds
Custom analog and mixed-signal blocks (PLL, ADC, DAC, LDO, etc.) and full chip layouts for HBM
Domain
Semiconductor / VLSI / Memory Technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IC layout design, LVS/DRC/Antenna verification, analog layout fundamentals (matching, EM, latch-up, IR-drop), design hierarchy understanding, tape-out support
Preferred skills
Experience with Temperature sensor, Charge Pump, Current Mirrors, Comparator, Differential Amplifier
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Perform layout verification (LVS/DRC/Antenna), guide junior team members in sub-block layouts, plan and schedule block-level layouts, communicate with global engineering teams
Seniority
Mid-Senior, hands-on IC