SR ENGINEER, HIG HBM LAYOUT
Core
Design and development of critical analog, mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Senior IC Layout Design Engineer
Builds
Custom analog/mixed-signal blocks (PLL, ADC, DAC, LDO, etc.) and full chip layouts for HBM
Domain
Semiconductor / VLSI / Memory
Required skills
IC layout design, LVS/DRC/Antenna verification, analog layout fundamentals, memory design hierarchy, physical verification, project planning
Preferred skills
Multiple tape-out support experience
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Design and develop critical analog, mixed-signal, custom digital blocks and full chip level integration; Perform layout verification (LVS/DRC/Antenna); Guide junior team members in sub-block-level layouts; Lead planning, area/time estimation, and scheduling for project milestones
Seniority
Senior, hands-on IC