Design Verification Engineer
Core
Own and execute functional verification for block-level and full-chip designs from specification through tape-out, focusing on DRAM and emerging memory architectures.
Role type
Senior IC design verification engineer (memory/storage)
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor / Memory and Storage
Required skills
SystemVerilog, UVM, constrained-random simulation, functional verification, coverage closure, RTL debugging, testbench architecture, verification planning
Preferred skills
Mentorship, verification methodology development, AI tool usage for verification
Technologies
SystemVerilog, UVM, simulation environments, verification tools
Responsibilities
Develop and maintain SystemVerilog/UVM-based testbenches, execute directed and constrained-random simulations, drive coverage closure, debug functional failures, collaborate with design engineers on RTL and specifications, provide verification status updates, contribute to verification tool and flow development, mentor junior engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
