Package Silicon Technology Node Development Director/DMTS
Core
Define and drive chip-package interaction (CPI) technology strategy and roadmaps to enable advanced silicon node transitions in next-generation memory products.
Role type
Director / Distinguished Member of Technical Staff (DMTS) in Package Development Engineering
Builds
Next-generation memory products (DRAM, NAND, NOR) enabling AI, 5G, data center, and mobile applications
Domain
Semiconductor manufacturing, memory technology, chip-package integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Chip-package interaction (CPI) strategy, semiconductor process technology development, failure mechanism analysis, reliability testing and qualification, risk management frameworks, cross-functional program leadership, technical roadmap planning
Preferred skills
Memory device physics, failure analysis techniques, qualification and screening methodologies, global technical initiative leadership
Technologies
Semiconductor packaging, memory technologies, failure analysis tools
Responsibilities
Define long-term CPI technology roadmaps aligned with advanced silicon node transitions; Drive technology strategy and risk management frameworks for future memory product launches; Lead global technical initiatives ensuring alignment between silicon, package, and test vehicle readiness; Partner with Fab Process Integration, Product Design, and Package Design teams to establish CPI risk identification and mitigation strategies; Align priorities, timelines, and resource planning with senior leadership; Serve as a subject matter expert in CPI failure mechanisms and reliability risks; Mentor engineering teams and represent PDE in strategic discussions
Seniority
Director level, strategic leadership with hands-on technical expertise